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How does the Z80 determine which peripheral sent an interrupt?
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How does the Z80 determine which peripheral sent an interrupt?
The Next CEO of Stack OverflowWhy does the Z80 have a half-carry bit?How fast is memcpy on the Z80?How can a C64 interrupt let the KERNAL keep operating?Which Z80 opcodes can I use without a stack?Why does the Z80 include the RLD and RRD instructions?Intel 8080 and Altair 8800. 256 I/0 ports, but only 7 free RST (interrupt subroutine) - how it works?Is it possible to switch the interrupt source of the C64 to VIC without changing the IRQ routine?Why do we need to acknowledge the interrupt from VIC-II?How do I Interface a PS/2 Keyboard without Modern Techniques?Where does the Z80 processor start executing from?
My understanding of how interrupts (and more specifically, interrupt daisy-chaining) works in the Z80 is limited, to say the least, so if I get anything wrong please correct me.
Anyway, let's say I have 2 PIO chips to control 2 different peripherals (lets say, a character LCD display, and some switches, but I'm sure that's not very relevant). I've connected the IEO pin of one PIO to the CPU's INT pin, and it's IEI pin to the other PIO's IEO. I then connected that PIO's IEI pin to a 5V rail. I got this information from this image: (but instead of the three different peripheral chips they use, I just have two PIO chips.)
[from here]
Anyway, my understanding is that this kind of configuration means that if the second PIO (the one directly connected to the 5V rail) pulls its IEO pin low, the other PIO will not be able to send an interrupt. Correct?
My issue is this: How would I cause a PIO chip's IEO pin to go low? And how can I actually send an interrupt from one of these peripherals? My initial thought would be that I'd just pull the CPU's INT pin low, but that doesn't make sense the more I think about it.
(On a side note, any idea what the INTACK pin is on that diagram?)
z80 interrupt
asked 5 hours ago
Jacob GarbyJacob Garby
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My understanding of how interrupts (and more specifically, interrupt daisy-chaining) works in the Z80 is limited, to say the least, so if I get anything wrong please correct me.
Anyway, let's say I have 2 PIO chips to control 2 different peripherals (lets say, a character LCD display, and some switches, but I'm sure that's not very relevant). I've connected the IEO pin of one PIO to the CPU's INT pin, and it's IEI pin to the other PIO's IEO. I then connected that PIO's IEI pin to a 5V rail. I got this information from this image: (but instead of the three different peripheral chips they use, I just have two PIO chips.)
[from here]
Anyway, my understanding is that this kind of configuration means that if the second PIO (the one directly connected to the 5V rail) pulls its IEO pin low, the other PIO will not be able to send an interrupt. Correct?
My issue is this: How would I cause a PIO chip's IEO pin to go low? And how can I actually send an interrupt from one of these peripherals? My initial thought would be that I'd just pull the CPU's INT pin low, but that doesn't make sense the more I think about it.
(On a side note, any idea what the INTACK pin is on that diagram?)
z80 interrupt
asked 5 hours ago
Jacob GarbyJacob Garby
2256
New contributor
Jacob Garby is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
add a comment |
My understanding of how interrupts (and more specifically, interrupt daisy-chaining) works in the Z80 is limited, to say the least, so if I get anything wrong please correct me.
Anyway, let's say I have 2 PIO chips to control 2 different peripherals (lets say, a character LCD display, and some switches, but I'm sure that's not very relevant). I've connected the IEO pin of one PIO to the CPU's INT pin, and it's IEI pin to the other PIO's IEO. I then connected that PIO's IEI pin to a 5V rail. I got this information from this image: (but instead of the three different peripheral chips they use, I just have two PIO chips.)
[from here]
Anyway, my understanding is that this kind of configuration means that if the second PIO (the one directly connected to the 5V rail) pulls its IEO pin low, the other PIO will not be able to send an interrupt. Correct?
My issue is this: How would I cause a PIO chip's IEO pin to go low? And how can I actually send an interrupt from one of these peripherals? My initial thought would be that I'd just pull the CPU's INT pin low, but that doesn't make sense the more I think about it.
(On a side note, any idea what the INTACK pin is on that diagram?)
z80 interrupt
asked 5 hours ago
Jacob GarbyJacob Garby
2256
New contributor
Jacob Garby is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
My understanding of how interrupts (and more specifically, interrupt daisy-chaining) works in the Z80 is limited, to say the least, so if I get anything wrong please correct me.
Anyway, let's say I have 2 PIO chips to control 2 different peripherals (lets say, a character LCD display, and some switches, but I'm sure that's not very relevant). I've connected the IEO pin of one PIO to the CPU's INT pin, and it's IEI pin to the other PIO's IEO. I then connected that PIO's IEI pin to a 5V rail. I got this information from this image: (but instead of the three different peripheral chips they use, I just have two PIO chips.)
[from here]
Anyway, my understanding is that this kind of configuration means that if the second PIO (the one directly connected to the 5V rail) pulls its IEO pin low, the other PIO will not be able to send an interrupt. Correct?
My issue is this: How would I cause a PIO chip's IEO pin to go low? And how can I actually send an interrupt from one of these peripherals? My initial thought would be that I'd just pull the CPU's INT pin low, but that doesn't make sense the more I think about it.
(On a side note, any idea what the INTACK pin is on that diagram?)
z80 interrupt
z80 interrupt
asked 5 hours ago
Jacob GarbyJacob Garby
2256
New contributor
Jacob Garby is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
asked 5 hours ago
Jacob GarbyJacob Garby
2256
New contributor
Jacob Garby is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
edited 5 hours ago
Jacob Garby
asked 5 hours ago
Jacob GarbyJacob Garby
2256
New contributor
Jacob Garby is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
asked 5 hours ago
Jacob GarbyJacob Garby
2256
asked 5 hours ago
Jacob GarbyJacob Garby
2256
2256
New contributor
Jacob Garby is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
New contributor
Jacob Garby is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
Jacob Garby is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
add a comment |
add a comment |
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You might want to consult the chapter for 'Interrupt Response' of the CPU manual (Chapter 8 on p.55 of the 1976 issue) and 'Interrupt Servicing' from the PIO manual (Chapter 6 on p.15 of the 1977 issue).
In general the Z80 supports 3 different interrupt modes:
Mode 0 - like 8080, here the interrupting device must place an instrution on the bus - usually done by a 8259 interrupt controller.
Mode 1 - All interrupts will jump to 38h (restart) and execute from there. Much like NMI
Mode 2 - Peripherals put an interrupt service number on the bus during interrupt response, the CPU uses for an indirect call thru a table of pointers in a 256 byte page pointed to by the I register.
The picture inserted hints that you intend to use Z80s Mode 2. To make it work:
- Write some service routine for your interrupt, ending in an RETI
- Disable interrupts
- Setup a vector table in a memory page (256 byte boundry)
- Pick any vector number you like (lets say 3)
- Put the address of your service routing to that vector (xx06/xx07)
- Put the vector number into the PIO channels vector register (control word with 2^0 set)
- Set the Interrupt control word (x7) for the port to define which bits and under wich configuration will trigger an interrupt. For example 97h FFh sent to Port A will make all inputs issue interrupts as soon as they go high.
- Set interrupt Mmode 2 of the CPU
- Enable interrupts
- Enjoy whatever happens :))
A Z80 in Mode 2 is perfect suited for an interrupt driven system.
How would I cause a PIO chip's IEO pin to go low?
Err ... by waiting for an interrupt to occur, then serving it?
(Maybe I do not really understand what part of information is missing).
answered 5 hours ago
RaffzahnRaffzahn
54.4k6133219
Okay, thanks! That cleared a lot of things up for me. I don't know if I'm being stupid, but one thing I don't understand is exactly how I would create an interrupt from the PIO -- I mean, how can I interrupt the CPU when a button is pressed, for example?
– Jacob Garby
4 hours ago
add a comment |
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You might want to consult the chapter for 'Interrupt Response' of the CPU manual (Chapter 8 on p.55 of the 1976 issue) and 'Interrupt Servicing' from the PIO manual (Chapter 6 on p.15 of the 1977 issue).
In general the Z80 supports 3 different interrupt modes:
Mode 0 - like 8080, here the interrupting device must place an instrution on the bus - usually done by a 8259 interrupt controller.
Mode 1 - All interrupts will jump to 38h (restart) and execute from there. Much like NMI
Mode 2 - Peripherals put an interrupt service number on the bus during interrupt response, the CPU uses for an indirect call thru a table of pointers in a 256 byte page pointed to by the I register.
The picture inserted hints that you intend to use Z80s Mode 2. To make it work:
- Write some service routine for your interrupt, ending in an RETI
- Disable interrupts
- Setup a vector table in a memory page (256 byte boundry)
- Pick any vector number you like (lets say 3)
- Put the address of your service routing to that vector (xx06/xx07)
- Put the vector number into the PIO channels vector register (control word with 2^0 set)
- Set the Interrupt control word (x7) for the port to define which bits and under wich configuration will trigger an interrupt. For example 97h FFh sent to Port A will make all inputs issue interrupts as soon as they go high.
- Set interrupt Mmode 2 of the CPU
- Enable interrupts
- Enjoy whatever happens :))
A Z80 in Mode 2 is perfect suited for an interrupt driven system.
How would I cause a PIO chip's IEO pin to go low?
Err ... by waiting for an interrupt to occur, then serving it?
(Maybe I do not really understand what part of information is missing).
answered 5 hours ago
RaffzahnRaffzahn
54.4k6133219
Okay, thanks! That cleared a lot of things up for me. I don't know if I'm being stupid, but one thing I don't understand is exactly how I would create an interrupt from the PIO -- I mean, how can I interrupt the CPU when a button is pressed, for example?
– Jacob Garby
4 hours ago
add a comment |
You might want to consult the chapter for 'Interrupt Response' of the CPU manual (Chapter 8 on p.55 of the 1976 issue) and 'Interrupt Servicing' from the PIO manual (Chapter 6 on p.15 of the 1977 issue).
In general the Z80 supports 3 different interrupt modes:
Mode 0 - like 8080, here the interrupting device must place an instrution on the bus - usually done by a 8259 interrupt controller.
Mode 1 - All interrupts will jump to 38h (restart) and execute from there. Much like NMI
Mode 2 - Peripherals put an interrupt service number on the bus during interrupt response, the CPU uses for an indirect call thru a table of pointers in a 256 byte page pointed to by the I register.
The picture inserted hints that you intend to use Z80s Mode 2. To make it work:
- Write some service routine for your interrupt, ending in an RETI
- Disable interrupts
- Setup a vector table in a memory page (256 byte boundry)
- Pick any vector number you like (lets say 3)
- Put the address of your service routing to that vector (xx06/xx07)
- Put the vector number into the PIO channels vector register (control word with 2^0 set)
- Set the Interrupt control word (x7) for the port to define which bits and under wich configuration will trigger an interrupt. For example 97h FFh sent to Port A will make all inputs issue interrupts as soon as they go high.
- Set interrupt Mmode 2 of the CPU
- Enable interrupts
- Enjoy whatever happens :))
A Z80 in Mode 2 is perfect suited for an interrupt driven system.
How would I cause a PIO chip's IEO pin to go low?
Err ... by waiting for an interrupt to occur, then serving it?
(Maybe I do not really understand what part of information is missing).
answered 5 hours ago
RaffzahnRaffzahn
54.4k6133219
Okay, thanks! That cleared a lot of things up for me. I don't know if I'm being stupid, but one thing I don't understand is exactly how I would create an interrupt from the PIO -- I mean, how can I interrupt the CPU when a button is pressed, for example?
– Jacob Garby
4 hours ago
add a comment |
You might want to consult the chapter for 'Interrupt Response' of the CPU manual (Chapter 8 on p.55 of the 1976 issue) and 'Interrupt Servicing' from the PIO manual (Chapter 6 on p.15 of the 1977 issue).
In general the Z80 supports 3 different interrupt modes:
Mode 0 - like 8080, here the interrupting device must place an instrution on the bus - usually done by a 8259 interrupt controller.
Mode 1 - All interrupts will jump to 38h (restart) and execute from there. Much like NMI
Mode 2 - Peripherals put an interrupt service number on the bus during interrupt response, the CPU uses for an indirect call thru a table of pointers in a 256 byte page pointed to by the I register.
The picture inserted hints that you intend to use Z80s Mode 2. To make it work:
- Write some service routine for your interrupt, ending in an RETI
- Disable interrupts
- Setup a vector table in a memory page (256 byte boundry)
- Pick any vector number you like (lets say 3)
- Put the address of your service routing to that vector (xx06/xx07)
- Put the vector number into the PIO channels vector register (control word with 2^0 set)
- Set the Interrupt control word (x7) for the port to define which bits and under wich configuration will trigger an interrupt. For example 97h FFh sent to Port A will make all inputs issue interrupts as soon as they go high.
- Set interrupt Mmode 2 of the CPU
- Enable interrupts
- Enjoy whatever happens :))
A Z80 in Mode 2 is perfect suited for an interrupt driven system.
How would I cause a PIO chip's IEO pin to go low?
Err ... by waiting for an interrupt to occur, then serving it?
(Maybe I do not really understand what part of information is missing).
answered 5 hours ago
RaffzahnRaffzahn
54.4k6133219
You might want to consult the chapter for 'Interrupt Response' of the CPU manual (Chapter 8 on p.55 of the 1976 issue) and 'Interrupt Servicing' from the PIO manual (Chapter 6 on p.15 of the 1977 issue).
In general the Z80 supports 3 different interrupt modes:
Mode 0 - like 8080, here the interrupting device must place an instrution on the bus - usually done by a 8259 interrupt controller.
Mode 1 - All interrupts will jump to 38h (restart) and execute from there. Much like NMI
Mode 2 - Peripherals put an interrupt service number on the bus during interrupt response, the CPU uses for an indirect call thru a table of pointers in a 256 byte page pointed to by the I register.
The picture inserted hints that you intend to use Z80s Mode 2. To make it work:
- Write some service routine for your interrupt, ending in an RETI
- Disable interrupts
- Setup a vector table in a memory page (256 byte boundry)
- Pick any vector number you like (lets say 3)
- Put the address of your service routing to that vector (xx06/xx07)
- Put the vector number into the PIO channels vector register (control word with 2^0 set)
- Set the Interrupt control word (x7) for the port to define which bits and under wich configuration will trigger an interrupt. For example 97h FFh sent to Port A will make all inputs issue interrupts as soon as they go high.
- Set interrupt Mmode 2 of the CPU
- Enable interrupts
- Enjoy whatever happens :))
A Z80 in Mode 2 is perfect suited for an interrupt driven system.
How would I cause a PIO chip's IEO pin to go low?
Err ... by waiting for an interrupt to occur, then serving it?
(Maybe I do not really understand what part of information is missing).
answered 5 hours ago
RaffzahnRaffzahn
54.4k6133219
answered 5 hours ago
RaffzahnRaffzahn
54.4k6133219
answered 5 hours ago
RaffzahnRaffzahn
54.4k6133219
answered 5 hours ago
RaffzahnRaffzahn
54.4k6133219
54.4k6133219
Okay, thanks! That cleared a lot of things up for me. I don't know if I'm being stupid, but one thing I don't understand is exactly how I would create an interrupt from the PIO -- I mean, how can I interrupt the CPU when a button is pressed, for example?
– Jacob Garby
4 hours ago
add a comment |
Okay, thanks! That cleared a lot of things up for me. I don't know if I'm being stupid, but one thing I don't understand is exactly how I would create an interrupt from the PIO -- I mean, how can I interrupt the CPU when a button is pressed, for example?
– Jacob Garby
4 hours ago
Okay, thanks! That cleared a lot of things up for me. I don't know if I'm being stupid, but one thing I don't understand is exactly how I would create an interrupt from the PIO -- I mean, how can I interrupt the CPU when a button is pressed, for example?
– Jacob Garby
4 hours ago
Okay, thanks! That cleared a lot of things up for me. I don't know if I'm being stupid, but one thing I don't understand is exactly how I would create an interrupt from the PIO -- I mean, how can I interrupt the CPU when a button is pressed, for example?
– Jacob Garby
4 hours ago
add a comment |
Jacob Garby is a new contributor. Be nice, and check out our Code of Conduct.
Jacob Garby is a new contributor. Be nice, and check out our Code of Conduct.
Jacob Garby is a new contributor. Be nice, and check out our Code of Conduct.
Jacob Garby is a new contributor. Be nice, and check out our Code of Conduct.
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